Verification Lead

Senior Verification Engineer – High-Speed NetworkingWe are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced SystemVerilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols.Key ResponsibilitiesDevelop and maintain UVM-based verification environmentsPerform constrained-random verification and coverage closureIntegrate and customize VIP for high-speed interfacesVerify protocols including 100Gb Ethernet, PCIe Gen5, and AMBA/AXIAutomate verification flows using Python and CI/CD pipelinesCollaborate with design and software teams; support bring-up using Vivado/VitisRequired SkillsStrong UVM and SystemVerilog verification experienceHigh-speed protocol knowledge: 100GbE, PCIe Gen5, AXIPython scripting and Git-based workflowsExperience with CI/CD in verification environmentsFamiliarity with AMD Vivado/Vitis tools

Created: 2026-01-30